1. Field
The present invention relates generally to integrated circuits, and more specifically to communication between master and slave components using a single wire bus interface.
2. Background
Wireless communication systems are widely deployed to provide various types of communication such as voice and data. Example wireless networks include cellular-based data systems. The following are several such examples: (1) the “TIA/EIA-95-B Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System” (the IS-95 standard), (2) the standard offered by a consortium named “3rd Generation Partnership Project” (3GPP) and embodied in a set of documents including Document Nos. 3G TS 25.211, 3G TS 25.212, 3G TS 25. 213, and 3G TS 25.214 (the W-CDMA standard), (3) the standard offered by a consortium named “3rd Generation Partnership Project 2” (3GPP2) and embodied in “TR-45.5 Physical Layer Standard for cdma2000 Spread Spectrum Systems” (the IS-2000 standard), and (4) the high data rate (HDR) system that conforms to the TIA/EIA/IS-856 standard (the IS-856 standard).
A wireless communication device commonly incorporates multiple components. For example, a baseband processor may interface with one or more Radio Frequency (RF) or other components. The baseband processor may generate and receive baseband signals, often in digital format. One or more Integrated Circuits (ICs) may be deployed to provide functions such as analog to digital conversion, digital to analog conversion, filtering, amplification, upconversion, downconversion, and many others. Various parameters and commands may be written to one or more slave devices by a master device (such as a baseband processor). The master device may need to receive (i.e. read) parameters and other data from one or more ancillary components (such as RFICs). Such configurations of master devices and slave devices may be deployed in devices outside of the communications field as well.
A Serial Bus Interface (SBI) protocol has been deployed in the prior art, which uses three signals to perform communication between a master device and one or more slave devices (i.e. a 3-wire interface). While the SBI protocol allows for multiple slaves to share one interface, some components have demonstrated sensitivity to activity of other components on a shared interface. Thus, some SBI interfaces have been deployed with a single master and a single slave device, to avoid such interference. Adding additional interfaces, as described, may require the addition of three pins (or pads) to the master device for each additional interface. This may add additional complexity and/or cost, due to increased die size, increased pin count, etc. It is therefore desirable to reduce the number of pins required to interface between a master device and a slave device.
There exist in the prior art a number of designs for master devices and slave devices that support the SBI interface. It may be desirable to provide for a new interface to communicate with existing SBI components, to increase interoperability, and to allow for new devices, either masters or slaves, to be phased into use with each other, as well as with legacy components. It is also desirable to provide a means for existing designs to be modified for communication on a reduced pin interface with a minimum amount of design time to increase time to market for new products and speed the rollout of the new interface.
There is therefore a need in the art for a single wire bus interface for communication between a master device and one or more slave devices. There is a further need for master devices, slave devices, and converters that interoperate with existing serial bus interfaces, such as those adapted to the SBI protocol.